When a plurality of memories provided on one chip of a semiconductor device are tested (self-tested) by a memory BIST (Built-In Self-Test) circuit provided on the same chip as the memories, there is some memories located far apart from the memory BIST circuit with regard to layout. The memory BIST circuit performs testing by generating and forcing a test vector comprising an address signal, control signals, and a write data to the memories under test and comparing read data from the memories under test with the write data.
When the memory located far apart from the memory BIST circuit is tested in the same way as a memory located close to the memory BIST circuit, timing margin in testing of the distant memory becomes tight due to wiring delay.
In Patent Document 1 (JP Patent Kokai Publication No. JP-P2006-155682A), when testing a plurality of memories provided in an LSI (Large Scale Integrated Circuit) using a memory BIST control circuit (referred to as a “memory BIST circuit”), a configuration shown in FIG. 3 is disclosed as an LSI test circuit for avoiding the above mentioned timing problems and carrying out an at-speed test, without depending on layout location relationships between the memory control BIST circuit and each of the memories. According to respective placement positions of memories 102 and 105, pipeline flip-flops 107 and 108 that when carrying out a memory BIST, delay a signal are inserted in a path connecting the memories to the memory BIST control circuit 106. For the memory 105 disposed at a location separated from the memory BIST control circuit 106 according to the configuration of the LSI circuit, signals between the memory and the memory BIST control circuit 106 are pipelined by the pipeline flip-flops 107 and 108, and a comparison is made of a test result at a timing that gives consideration to the number of pipeline stages in the memory control BIST circuit 106.
[Patent Document 1]
    JP Patent Kokai Publication No. JP-P2006-155682A (FIG. 1)